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TLE7273-2 low dropout voltage regulator data sheet, rev. 1.2, april 2009 automotive power www..net
type package marking TLE7273-2gv50 pg-dso-14 TLE7273-2gv50 TLE7273-2gv33 pg-dso-14 TLE7273-2gv33 TLE7273-2gv26 pg-dso-14 TLE7273-2gv26 TLE7273-2ev50 pg-ssop-14 exposed pad 7273 v50 pg-dso-14 pg-ssop-14 exposed pad data sheet 2 rev. 1.2, 2009-04-28 low dropout voltage regulator TLE7273-2 1overview features ? output voltage 5 v, 3.3 v or 2.6 v ? output voltage tolerance 2% up to 180ma ? ultra low quiescent cu rrent consumption < 36 a ? enable function ? very low dropout voltage ? reset with adjustab le power-on delay ? window watchdog with current dependent deactivation ? output current limitation ? wide operation range up to 45 v ? wide temperature range from -40 c to 150 c ? overtemperature shutdown ? green product (rohs compliant) ? aec qualified description the TLE7273-2 is a monolithic voltage regulator with integrated window watchdog and reset dedicated for microcontroller supplies under harsh automotive environment conditions. due to its ultra low quiescent current, the TLE7273-2 is perfectly suited for applications that are permanently connected to battery. in addition, the regulator can be shut down via the enable input causing the current consumption to drop below 3 a. the TLE7273-2 is equipped with an output current limitation and an overtemperature shutdown, prot ecting the device against overload, short ci rcuit and over-temperature. it operates in the wide junction temperature range from -40 c to 150 c.
data sheet 3 rev. 1.2, 2009-04-28 TLE7273-2 block diagram 2block diagram wd i wm 1 reset gener ator and wi ndow watchdog enabl e char ge pump TLE7273-2 over temper atur e shutdown bandgap refer ence 1 en q ro wm 2 i gnd figure 1 block diagram
TLE7273-2 pin configuration data sheet 4 rev. 1.2, 2009-04-28 3 pin configuration 3.1 pin assignment (pg-dso-14) en gnd wm1 wm2 gnd 8 wdi 12 11 gnd gnd 1 2 3 4 5 gnd 6 7 14 13 ro gnd 9 10 aep02113_7273 gnd i q figure 2 pin assignment pg-dso-14 (top view) 3.2 pin definitions an d functions (pg-dso-14) table 1 pin definitions and functions pin no. symbol function 1 ro reset output TLE7273-2gv33, TLE7273-2gv26: open drain output; TLE7273-2gv50: integrated 20 k pull-up resistor to output q; leave open if not needed 2-5, 10-12 gnd ground connect pin 2 and 3 to gnd; connect pin 4-5 and 10-12 to heat sink area with gnd potential 7 wm1 watchdog mode bit 1 watchdog and reset mode selection, see ?window watchdog state diagram, watchdog and reset modes? on page 9 ; connect to q or gnd 6 wm2 watchdog mode bit 2 watchdog and reset mode selection, see ?window watchdog state diagram, watchdog and reset modes? on page 9 ; connect to q or gnd 8 wdi watchdog input trigger input for watchdog pulses; to turn off watchdog connect to gnd and connect pin wm1 and wm2 to q 9 q output voltage block to gnd with a ceramic capacitor cl ose to the ic terminals, respecting the values given for its capacitance and esr in ?functional range? on page 7 13 i input voltage block to ground directly at the ic with a 100 nf ceramic capacitor 14 en enable input low level disables the ic; integrated pull-down resistor to gnd
data sheet 5 rev. 1.2, 2009-04-28 TLE7273-2 pin configuration 3.3 pin assignments (pg-ssop-14 exposed pad) (1 :', 4 qf qf qf , 52 :0 :0 *1' qf qf *1' 7/(b3,1&21),*b6623 69* figure 3 pin assignment pg-ssop-14 exposed pad (top view) 3.4 pin definitions an d functions (pg-ssop-14 exposed pad) table 2 pin definitions and functions pin no. symbol function 1 ro reset output integrated 20 k ? 22) 2 2 2 2 v q or gnd 7 wm1 watchdog mode bit 1 watchdog and reset mode selection, see figure 5 ; connect to v q or gnd 8 wdi watchdog input trigger input for watchdog pulses; pull down to gnd if not needed and turn off the watchdog with wm1 and wm2 pin 9 q output voltage block to gnd with a ceramic capacitor c q
TLE7273-2 general product characteristics data sheet 6 rev. 1.2, 2009-04-28 4 general product characteristics 4.1 absolute maximum ratings table 3 absolute maximum ratings 1) 1) not subject to production test, specified by design -40 < t j < 150 v i -0.3 45 v ? voltage v q -0.3 5.5 v permanent voltage v q -0.3 6.2 v t < 10 s 2) exposure to these absolute maximum ratings for extended periods ( t > 10 s) may affect device reliability voltage v en -1 45 v ? current i en -1 1 ma ? voltage v ro -1 7 v permanent voltage v wm1 -0.3 5.5 v permanent voltage v wm1 -0.3 6.2 v t < 10 s 2) current i wm1 -5 5 ma ? human body model (hbm) 3) esd hbm test according jedec jesd22-a114 3) voltage - 3 kv ? charged device model (cdm) 4) esd cdm test according aec/esda esd-stm5.3.1-1999 4) voltage - 1.5 kv ? temperatures junction temperature t j -40 150 t stg -50 150 2) note: maximum ratings are absolute ratings; exceeding an y one of these values may cause irreversible damage to the integrated circuit. integrated protection functions are designed to prevent ic destruction under fault conditions. fault conditions are considered as outsid e normal operating range. pr otections functions are not designed for continuous repetitive operation. input i 4.1.1 output q, reset output ro, watchdog mode 2 4.1.2 4.1.3 enable input en 4.1.4 4.1.5 watchdog input wdi 4.1.6 watchdog mode 1 4.1.7 4.1.8 4.1.9 esd susceptibility 4.1.10 4.1.11 4.1.12 4.1.13
data sheet 7 rev. 1.2, 2009-04-28 TLE7273-2 general product characteristics 4.2 functional range pos. parameter symbol limit values unit remarks min. max. input voltage v i 5.5 45 v TLE7273-2gv50, TLE7273-2ev50 4.2 45 v TLE7273-2gv33 4.5 45 v TLE7273-2gv26 output capacitor?s requirements for stability c q 470 ? nf 1) the minimum output capacitance requirement is appl icable for a worst case capacitance tolerance of 30% esr(c q ) ? 3 ? 2) f = 10 khz ? 2) ) note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 4.3 thermal resistances pos. parameter symbol limit values unit remarks min. typ. max. junction to soldering point 1) not subject to production test, specified by design 1) r thjsp ? 30 ? k/w measured to group of pins 3, 4, 5, 10, 11, 12 junction to ambient 1) r thja ? 53 ? k/w 2) specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board wi th 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. ? 105 ? k/w footprint only 3) specified r thja value is according to jedec jesd 51-3 at nat ural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 ) 2 ) 2 ) ) r thjsp ? 14 ? k/w measured to exposed pad junction to ambient 1) r thja ? 47 ? k/w 2) ? 141 ? k/w footprint only 3) ? 66 ? k/w 300 mm 2 heatsink area on pcb 3) ? 56 ? k/w 600 mm 2 heatsink area on pcb 3) 3) 2) 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 package pg-dso-14 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 package pg-ssop-14 exposed pad 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10
TLE7273-2 block description and electrical characteristics data sheet 8 rev. 1.2, 2009-04-28 5 block description and el ectrical characteristics 5.1 description 5.1.1 power on reset and reset output for an output voltage level of v q v q reaches the reset threshold v rt , the signal at ro remains low for the power-up reset delay time t rd . the reset function and timing is illustrated in figure 4 . the reset reaction time t rr avoids wrong triggering caused by short ?glitches? on the v q - line. in case of v q power down ( v q < v rt for t > t rr ) a logic low signal is generated at the pin ro to reset an external microcontroller. the TLE7273-2gv50 and TLE7273-2ev50 feature an integr ated pull-up resistor on the reset output while the TLE7273-2gv33 and TLE7273-2gv26 have an open drain ou tput requiring an external pull-up resistor. when connected to a voltage level of 5 v, a recommended value for this external resistor is ? v ext = 5 v): r extmin = ? v / i ro = ( v ext - v romin ) / i ro = (5 v - 0.25 v) / 1.0 ma = 4.75 k ? v q < 1 v the integrated pull-up resistor of the TLE7273-2gv50 is switched off setting the reset output high ohmic. v i aet03526new.vsd t v q t v rt < t rr v ro t v rol v roh t rd t rr v rti t rr figure 4 reset function and timing diagram 5.1.2 watchdog operation the watchdog uses a fraction of the ch arge pump oscillator?s clock signal as timebase. the wa tchdog timebase can be adjusted using the pins wm1 and wm2 (see figure 5 ). the watchdog can be turned off setting wm1 and wm2 to high level. the timing values refer to typ. va lues with wm1 and wm2 connected to gnd (fast watchdog and reset timing). figure 5 shows the state diagram of the window watchdog ( wwd) and the watchdog and reset mode selection. after power-on, the reset output signal at the ro pin (microcontroller reset) is kept low for the reset delay time t rd of typ. 16 ms. with the low to high transition of the signal at ro t he device starts the ignore window time t cw (32 ms). during this window the signal at the wdi pin is ignored. next the wwd starts the open window which
data sheet 9 rev. 1.2, 2009-04-28 TLE7273-2 block description and electrical characteristics is in the very first turn after power up a long open window with tmax = 4 * t ow . in the following turns, the timing corresponds to the standard timing sett ing as described in the specification. when a valid trigger signal is detected during the open win dow a closed window is initia lized immediately. a trigger signal within the closed window is interpreted as a pretrigg er failure and results in a re set. after the closed window the open window with the duration t ow is started again. the open window la sts at minimum until the trigger process has occurred, at maximum t ow is 32 ms (typ. value with fast timing). t sam typ. 0.5 ms) are decoded as a valid trigger . a reset is generated (ro goes low) if there is no tri gger pulse during the open window or if a pretrigger occurs during the closed window. the triggering is correct also, if the first three samples (t wo high one low) of the trigger pulse at pin wdi are inside the closed window and only the fourth sample (the second low sample) is taken in the open window. after turning off the watchdog by outp ut current reduction, ro remains high. (see also the signal diagram in figure 6 ). after turning on the wwd again by exceeding the current threshold, the logic cycle starts again with the ignore window and goes then into the ?1st. long open window?. this 1st long ow is maximum 4 * t ow long and allows the re-synchronisation between the micro controlle r and the wwd timing. the 1st. long ow is closed by the first valid trigger on wdi from the mirco controller. this trigger ensures the synchronisation. as soon as this trigger is done, the micro controller timing must be stable and correspondent to t wd . aea03527_1.vsd no trigger closed window open window trigger wm1 llhh wm2 l h l h window watchdog mode fast slow fast off reset trigger ignore window always always no trigger during open window trigger during closed window reset mode fast slow slow slow watchdog off iq > 5ma always iq < 0.5ma figure 5 window watchdog state diagram, watchdog and reset modes
t vi/v vq/v vro/v wnd wdi/v t rd ingnore wnd v rt 1. correct trigger no trigger in ow t rr t t t t ow cw t rr cw (wrong) trigger in cw t wd,p 1. long ow 1. long ow 1. long ow t rd power fail iq/a t t rd ow cw i q, wd_on 1. long ow i q, wd_off current controlled wd-turn off 1st long open window to synchronize wd ow cw no reset during current shut down normal operation don?t care wdi during iw TLE7273-2 block description and electrical characteristics data sheet 10 rev. 1.2, 2009-04-28 figure 6 window watchdog signal diagram aet02952 watchdog trigger signal valid not valid = watchdog decoder sample point ecw t closed window wdi wdi open window eow t open window closed window figure 7 window watchdog definitions
data sheet 11 rev. 1.2, 2009-04-28 TLE7273-2 block description and electrical characteristics 5.2 electrical characteristics electrical characteristics v i =13.5 v; ? 40 c < t j < 150 c; unless otherwise specified pos. parameter symbol limit values unit test condition min. typ. max. output q 5.2.1 output voltage v q 4.90 5.00 5.10 v TLE7273-2gv50, TLE7273-2ev50 1 ma < i q < 180 ma 6 v < v i < 16 v 5.2.2 output voltage v q 4.90 5.00 5.10 v TLE7273-2gv50, TLE7273-2ev50 i q = 10 ma 6 v < v i < 45 v 5.2.3 output voltage v q 3.234 3.30 3.366 v TLE7273-2gv33 1 ma < i q < 180 ma 4.5 v < v i < 16 v 5.2.4 output voltage v q 3.234 3.30 3.366 v TLE7273-2gv33 i q = 10 ma 4.5 v < v i < 45 v 5.2.5 output voltage v q 2.548 2.60 2.652 v TLE7273-2gv26 1 ma < i q < 180 ma 4.5 v < v i < 16 v 5.2.6 output voltage v q 2.548 2.60 2.652 v TLE7273-2gv26 i q = 10 ma 4.5 v < v i < 45 v 5.2.7 output current limitation i q 200 ? 500 ma v q = 2.0 v 5.2.8 200 ? 600 v q = 0 v 5.2.9 dropout voltage 1) dr = v i ? v q v dr ? 250 500 mv i q = 180 ma TLE7273-2gv50, TLE7273-2ev50 5.2.10 load regulation ? q,lo ? 50 90 mv 1 ma < i q < 180 ma; 5.2.11 line regulation ? q,li ? 10 50 mv i q = 1 ma; 10 v < v i < 32 v 5.2.12 power supply ripple rejection psrr ? 60 ? db f r = 100 hz; v r = 0.5 v pp 5.2.13 reverse output current clamping v q ? ? 5.5 v i q = -1 ma, v en = 0 v current consumption 5.2.14 quiescent current q = i i ? i q i q ? 28 36 a i q = 100 a; j < 80c 5.2.15 quiescent current disabled i q ? 1 3 a v en = 0v; t j < 80c enable input en 5.2.16 high level input voltage v en,h 3.0 ? ? v v q on
TLE7273-2 block description and electrical characteristics data sheet 12 rev. 1.2, 2009-04-28 5.2.17 low level input voltage v en,l ? ? 0.5 v v q = 0.02 v; i q = 5 ma; j < 125 c 5.2.18 ? ? 0.3 v v q = 0.02 v; i q = 5 ma 5.2.19 high level input current i en,h ? 3 4 a v en = 5 v watchdog mode bit 1 5.2.20 high level input voltage v wm1,h 4.00 ? ? v TLE7273-2gv50, TLE7273-2ev50 5.2.21 2.65 ? ? v TLE7273-2gv33 5.2.22 2.30 ? ? v TLE7273-2gv26 5.2.23 low level input voltage v wm1,l ? ? 0.80 v watchdog mode bit 2 5.2.24 high level input voltage v wm2,h 4.00 ? ? v TLE7273-2gv50, TLE7273-2ev50 5.2.25 2.65 ? ? v TLE7273-2gv33 5.2.26 2.30 ? ? v TLE7273-2gv26 5.2.27 low level input voltage v wm2,l ? ? 0.80 v watchdog input wdi 5.2.28 high level input voltage v wdi,h 4.00 ? ? v TLE7273-2gv50, TLE7273-2ev50 5.2.29 2.65 ? ? v TLE7273-2gv33 5.2.30 2.30 ? ? v TLE7273-2gv26 5.2.31 low level input voltage v wdi,l ? ? 0.80 v 5.2.32 high level input current i wdi,h ? 3 4 a v wdi = 5 v 5.2.33 low level input current i wd,il ? 0.5 1 a v wdi = 0 v t j < 80 c 5.2.34 watchdog sampling time t sam 0.40 0.50 0.60 ms fast watchdog timing 5.2.35 0.80 1.00 1.20 ms slow watchdog timing 5.2.36 ignore window time t iw 25.6 32.0 38.4 ms fast watchdog timing 5.2.37 51.2 64.0 76.8 ms slow watchdog timing 5.2.38 open window time t ow 25.6 32.0 38.4 ms fast watchdog timing 5.2.39 51.2 64.0 76.8 ms slow watchdog timing 5.2.40 closed window time t cw 25.6 32.0 38.4 ms fast watchdog timing 5.2.41 51.2 64.0 76.8 ms slow watchdog timing 5.2.42 window watchdog trigger time 2) t wd ? 48 ? ms fast watchdog timing 5.2.43 ? 96 ? ms slow watchdog timing electrical characteristics v i =13.5 v; ? 40 c < t j < 150 c; unless otherwise specified pos. parameter symbol limit values unit test condition min. typ. max.
data sheet 13 rev. 1.2, 2009-04-28 TLE7273-2 block description and electrical characteristics 5.2.44 watchdog deactivation current threshold i q,wd_off 0.50 ? ? ma i q decreasing v i > 5.5v for TLE7273-2gv50, TLE7273-2ev50 i > 4.5v for tle7273- 2gv33, TLE7273-2gv26 5.2.45 watchdog activating current threshold i q,wd_on ? ? 5 ma i q increasing v i > 5.5v for TLE7273-2gv50, TLE7273-2ev50 v i > 4.5v for tle7273- 2gv33, TLE7273-2gv26 reset output ro 5.2.46 output undervoltage reset switching threshold v rt 4.50 4.60 4.70 v TLE7273-2gv50, TLE7273-2ev50 v q decreasing 5.2.47 3.00 3.07 3.13 v TLE7273-2gv33 3) v i > 4.5v; v q decreasing 5.2.48 2.35 2.38 2.45 v TLE7273-2gv26 3) v i > 4.5v; v q decreasing 5.2.49 input undervoltage reset switching threshold v rti ? 3.9 4.0 v TLE7273-2gv26 3) TLE7273-2gv33 3) v q > v rt ; v i decreasing 5.2.50 5.2.51 5.2.52 output undervoltage reset hysteresis v rh ? 45 ? mv TLE7273-2gv26 5.2.53 output undervoltage reset hysteresis v rh ? 60 ? mv TLE7273-2gv33 5.2.54 ? 90 ? mv TLE7273-2gv50, TLE7273-2ev50 5.2.55 maximum reset sink current i ro,max 1.75 ? ? ma TLE7273-2gv50, TLE7273-2ev50 v q = 4.5 v; v ro =0.25 v 5.2.56 1.3 ? ? ma TLE7273-2gv33 v q = 3.0 v; v ro = 0.25 v 5.2.57 1.0 ? ? ma TLE7273-2gv26 v q = 2.35v; v ro = 0.25v electrical characteristics v i =13.5 v; ? 40 c < t j < 150 c; unless otherwise specified pos. parameter symbol limit values unit test condition min. typ. max.
TLE7273-2 block description and electrical characteristics data sheet 14 rev. 1.2, 2009-04-28 5.2.58 reset output low level voltage v rol ? 0.15 0.25 v v q 1 v; i ro < 200 a 5.2.59 reset output high level voltage v roh 4.5 ? ? v TLE7273-2gv50, TLE7273-2ev50 5.2.60 reset high level leakage current i rolk ? ? 1 a TLE7273-2gv33 TLE7273-2gv26 5.2.61 integrated reset pull up resistor r ro 10 20 40 k ? TLE7273-2gv50, TLE7273-2ev50 internally connected to v q 5.2.62 power-on reset delay time t rd 12.8 16.0 19.2 ms fast reset timing 5.2.63 25.6 32.0 38.4 ms slow reset timing 5.2.64 reset reaction time t rr - 4 12 s 1) measured when the output voltage has dropped 100 mv from the nominal value obtained at v i = 13.5 v 2) recommendation for typical trigger time; t wd = t cw + 1/2* t ow 3) reset output triggered when output voltage v q is lower than output voltage reset switching threshold v rt or is also triggered, when input voltage is decreasing to v i < 4.0 v and v q > v rt electrical characteristics v i =13.5 v; ? 40 c < t j < 150 c; unless otherwise specified pos. parameter symbol limit values unit test condition min. typ. max.
typical performanc e characteristics 1_iq-tj.vsd 10 1 0.01 100 i q [a] -40 t j [c] -20 20 40 80 100 0 60 140 120 v i = 13.5v i q = 100 a current consumption i q versus t j (en=on) current consumption i q versus 2 2 2 i q [m a] i q [a] t j = -40 c t j = 25 c output current i q (en=on) data sheet 15 rev. 1.2, 2009-04-28 TLE7273-2 current consumption i q versus v i at t j =25c (en=on) current consumption i q versus v i at t j =-40c (en=on) 0 v i [v ] 20 30 i q [a ] 3a_iq-vi_25.vsd 100 50 150 10 40 i q = 0.2ma i q = 10ma i q = 100ma t j = 25 c 200 0 v i [v ] 20 30 i q [a ] 3a_iq-vi_-40.vsd 100 50 150 10 40 i q = 0.2ma i q = 10ma i q = 100ma t j = -40c 200
typical performance characteristics (contd) 0 i q [ma] 100 ? v q [mv] 18a_dvq-diq_vi6v.vsd -2 -3 -4 200 0 t j = 25 c -5 v i = 6v t j = -40 c t j = 150 c -6 load regulation d v q versus i q i q [ma] ? v q [mv] 18c_dvq-diq_vi28v.vsd t j = 25 c v i = 28 t j = -40 c t j = 150 c 0100 -2 -3 -4 200 0 -5 -6 load regulation d v q versus i q TLE7273-2 data sheet 16 rev. 1.2, 2009-04-28 load regulation d v q versus i q power supply ripple rejection psrr i q [ma] ? v q [mv] 18b_dvq-diq_vi135v.vsd t j = 25 c v i = 13.5v t j = -40 c t j = 150 c -2 -3 -4 0 -5 -6 0 100 200 10 f [hz] 10k psrr [db] 13_psrr.vsd 60 50 100 1k 100k 80 30 40 i q = 10 ma v ripple = 1 v v in = 13.5 v c q = 470nf ceramics t j = 25 c i q = 100 ma i q = 0.1 ma
typical performance characteristics (contd) 0 v i [v] 515203035 ? v q [mv] 19_dvq-dvi_25c_.vsd 10 25 45 40 t j = 25 c i q = 100ma i q = 1ma 0 -2 -4 2 6 -6 i q = 10ma line regulation d v q versus v i i en [a] 24_iinh vs vinh.vsd 30 20 10 40 t j = 25c 10 v en [v] 30 40 20 50 t j = -40c t j = 150c enable input current i en versus v en data sheet 17 rev. 1.2, 2009-04-28 TLE7273-2 line regulation d v q versus v i line regulation d v q versus v i 0 v i [v] 515203035 ? v q [mv] 19_dvq-dvi_-40c.vsd 10 25 45 40 t j = -40 c i q = 10ma i q = 100ma i q = 1ma 0 -2 -4 2 6 -6 0 v i [v] 515203035 ? v q [mv] 19_dvq-dvi__150c.vsd 0 -2 -4 2 10 25 45 40 6 t j = 150 c -6 i q = 10ma i q = 1ma
typical performance characteristics (contd) v en [v] 25a_vinh_tj_ inh_on.vsd 1.5 1.0 0.5 2.0 2.5 v i = 13.5v v en increasing -40 t j [c] -20 20 40 80 100 060 140 120 v en decreasing enable high level / low level input voltage v en,h / v en,l versus junction temperature t j -40 t j [c] -20 20 40 80 100 ? v [mv] 29_vrt_hysteresis-_vs_temp_5v.vsd 60 40 20 80 060 140 120 v i = 13.5 v 120 reset hysteresis versus t j (5v-version) TLE7273-2 data sheet 18 rev. 1.2, 2009-04-28 enable input current i en versus v i , en=off reset threshold v rt versus t j (5v-version) i en [a] 25_iinh vs vin inh_off.vsd 0.6 0.4 0.2 0.8 t j = 25c 10 v in [v] 30 40 20 1.0 t j = -40c t j = 150c en = off -40 t j [c] -20 20 40 80 100 v q [v] 26_vrt_vs_temp_5v.vsd 4.80 4.70 4.60 4.90 060 140 120 v i = 13.5 v reset release threshold reset trigger threshold
data sheet 19 rev. 1.2, 2009-04-28 TLE7273-2 typical performance characteristics (contd) reset threshold v rt versus t j (3.3v-version) reset hysteresis versus t j (3.3v-version) -40 t j [c] -20 20 40 80 100 ? v [mv] 29_vrt_hysteresis-_vs_temp_33v.vsd 60 40 20 80 060 140 120 v i = 13.5 v 120 reset threshold v rt versus t j (2.6v-version) reset hysteresis versus t j (2.6v-version) -40 t j [c] -20 20 40 80 100 v q [v] 26_vrt_vs_temp_33v.vsd 3.10 3.00 2.90 3.20 060 140 120 v i = 13.5 v reset release threshold reset trigger threshold -40 t j [c] -20 20 40 80 100 v q [v] 26_vrt_vs_temp_26v.vsd 2.40 2.30 2.20 2.50 060 140 120 v i = 13.5 v reset release threshold reset trigger threshold -40 t j [c] -20 20 40 80 100 ? v [mv] 29_vrt_hysteresis-_vs_temp_26v.vs d 60 40 20 80 060 140 120 v i = 13.5 v 120
-40 t j [c] -20 20 40 80 100 t rr [s] 28_resetreaction_vs_temp.vsd 6 4 2 8 0 60 140 120 v i = 13.5 v 12 TLE7273-2 data sheet 20 rev. 1.2, 2009-04-28 reset reaction time t rr versus junction temperature t j -40 t j [c] -20 20 40 80 100 t wd [ms] 44_twd_vs_temp.vsd 50 40 30 60 060 140 120 v i = 13.5 v 80 timing for ignore-, open- closed- window fast timing slow timing reset delay t rd time versus junction temperature t j reset output sink current i ro versus junction temperature t j watchdog timing t wd versus junction temperature t j typical performance characteristics (contd) -40 t j [c] -20 20 40 80 100 t rd [ms] 27_resetdelay vs temp.vsd 30 20 10 40 060 140 120 v i = 13.5 v 60 slow timing fast timing -40 t j [c] -20 20 40 80 100 i ro [ma] 30_iro_vs_temp.vsd 3,20 2,80 2,40 3,60 0 60 140 120 v i = 13.5 v 4,40
typical performance characteristics (contd) 12_esr-iq.vsd 1 0.1 0.01 esr cq [ ? i q [ma] 100 200 c q = 470nf t j = -40...150 c 100 10 stable region region of stability esr ( c q ) versus i q data sheet 21 rev. 1.2, 2009-04-28 TLE7273-2
TLE7273-2 package outlines data sheet 22 rev. 1.2, 2009-04-28 6 package outlines 1) does not include plastic or metal protrusion of 0.15 max. per side 2) lead width can be 0.61 max. in dambar area -0.2 8.75 1) 0.64 0.19 +0.06 index marking 1.27 +0.10 0.41 0.1 1 14 2) 7 14x 8 0.175 (1.47) 0.07 ?.2 6 0.35 x 45? -0.2 1.75 max. 4 1) ?.25 8?max. -0.06 0.2 m ab m 0.2 c c b a gps01230 gps01230.eps figure 8pg-dso-14
pg-ssop-14-1,-2,-3-po v02 1 7 14 8 14 17 8 14x 0.25 ?.05 2) m 0.15 d c a-b 0.65 c stand off 0 ... 0.1 (1.45) 1.7 max. 0.08 c a b 4.9 ?.1 1) a-b c 0.1 2x 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include dambar protrusion bottom view ?.2 3 ?.2 2.65 0.2 ?.2 d 6 m d 8x 0.64 ?.25 3.9 ?.1 1) 0.35 x 45? 0.1 cd +0.06 0.19 8 ? max. index marking exposed diepad data sheet 23 rev. 1.2, 2009-04-28 TLE7273-2 package outlines figure 9pg-ssop-14 exposed pad green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. gree n products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). you can find all of our packages, so rts of packing and others in our
TLE7273-2 revision history data sheet 24 rev. 1.2, 2009-04-28 7 revision history revision date changes 1.2 2009-04-28 2.6v version, 5v version in pg-ssop-14 package and all related description added: in ?features? on page 2 ?or 2.6 v? added in ?features? on page 2 package drawing for pg-dso-14 updated, package drawing for pg-ssop-14 added in ?overview? on page 2 in table at the bottom type ?TLE7273-2gv26? and ?TLE7273-2ev50? added in ?pin definitions and functions (pg-dso-14)? on page 4 in description for pin 1 ?, TLE7273-2gv26? added ?pin assignments (pg-ssop-14 exposed pad)? on page 5 and ?pin definitions and functions (pg-ssop-14 exposed pad)? on page 5 added; in ?functional range? on page 7 item 4.2.3 added, in item 4.2.1 ?, tle7273- 2ev50? added; in ?thermal resistances? on page 7 values for pg-ssop-14 package added: item 4.3.6 , item 4.3.7 , item 4.3.8 , item 4.3.9 and item 4.3.10 added in ?power on reset and reset output? on page 8 ?TLE7273-2ev50? in description added in ?electrical characteristics? on page 11 all specific items for 2.6v version added: item 5.2.5 , item 5.2.6 , item 5.2.22 , item 5.2.26 , item 5.2.30 , item 5.2.48 , item 5.2.52 and item 5.2.57 added; in item 5.2.44 , item 5.2.45 , item 5.2.49 , item 5.2.50 , item 5.2.51 and item 5.2.60 conditions for 2.6v version added; in item 5.2.1 , item 5.2.2 , item 5.2.9 , item 5.2.20 , item 5.2.24 , item 5.2.28 , item 5.2.44 , item 5.2.45 , item 5.2.46 , item 5.2.54 , item 5.2.55 , item 5.2.59 and item 5.2.61 ?, TLE7273-2ev50? added in ?typical performance characteristics? on page 15 graphs ?reset threshold vrt versus junction temperature tj (3.3v-version)? on page 19 , ?reset threshold vrt versus junction temperature tj (3.3v-version)? on page 19 , ?reset threshold vrt versus junction temperature tj (2.6v- version)? on page 19 and ?reset hysteresis versus junction temperature tj (3.3v-version)? on page 19 added in ?package outlines? on page 22 oulines for pg-ssop-14 added: figure 9
data sheet 25 rev. 1.2, 2009-04-28 TLE7273-2 revision history 1.1 2008-07-25 3.3v version and all related description added: in ?features? on page 2 ?3.3v? added in ?overview? on page 2 in table at the bottom type ?TLE7273-2gv33? added in ?pin definitions and functions (pg-dso-14)? on page 4 in description for pin 1 ?TLE7273-2gv33: open drain output;? added in ?functional range? on page 7 item 4.2.2 added in ?power on reset and reset output? on page 8 description for dimensioning external pull-up resistor at ro added; in ?electrical characteristics? on page 11 all specific items for 3.3v version added: item 5.2.3 , item 5.2.4 , item 5.2.21 , item 5.2.25 , item 5.2.29 , item 5.2.47 , item 5.2.49 , item 5.2.50 , item 5.2.51 , item 5.2.53 , item 5.2.56 and item 5.2.60 added; in item 5.2.44 and item 5.2.45 conditions for 3.3v version added; 1.0 2008-04-10 final version data sheet revision date changes
edition 2009-04-28 published by infineon technologies ag 81726 munich, germany ? 2009 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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